项目描述 ：
This repository has a quick documentation covering the basics of RTL Design using verilog using the open source Skywater 130nm PDK. This covers the basics of RTL Design using Verilog and simulation, Logic synthesis and optimisations

高级语言： Verilog

项目主页：

项目地址: git://github.com/shariethernet/RTL-design-using-Verilog-with-SKY130-Technology.git

创建时间： 2021-06-02T18:29:56Z
项目社区：https://github.com/shariethernet/RTL-design-using-Verilog-with-SKY130-Technology
开源协议：
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