Xedge TTL640x480 返回
项目作者： SmallRoomLabs

项目描述 ：
Low chip count 74xx-logic generating a proper 640x480 VGA sync/blanking signals
高级语言： Prolog
项目地址: git://github.com/SmallRoomLabs/TTL640x480.git
创建时间： 2019-09-20T08:18:11Z
项目社区：https://github.com/SmallRoomLabs/TTL640x480
开源协议：MIT License
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Documentation_de_1647965249415.pdf
Documentation_en_1647965249537.pdf
Documentation_es_1647965249675.pdf
Documentation_pt_1647965249810.pdf
TTL640x480-schematics_1647965250353.pdf
TTL640x480-schematics_1650678774922.pdf
Documentation_de_1650678772974.pdf
Documentation_en_1650678773070.pdf
Documentation_es_1650678773169.pdf
Documentation_pt_1650678773212.pdf