项目描述 ：
Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual files. Download the project and run the main project file.

高级语言： Verilog

项目主页：

项目地址: git://github.com/MostafaOkasha/ECHO-and-FIR-FILTER-implementation-on-Verilog-HDL.git

创建时间： 2017-03-16T03:18:30Z
项目社区：https://github.com/MostafaOkasha/ECHO-and-FIR-FILTER-implementation-on-Verilog-HDL
开源协议：
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