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FPGA/ASIC
MU0_project
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项目作者:
fabiano77
项目描述 :
This project is to design a processor and memory in the digital system design course at university.
高级语言:
Verilog
项目主页:
项目地址:
git://github.com/fabiano77/MU0_project.git
创建时间:
2020-11-28T09:50:48Z
项目社区:
https://github.com/fabiano77/MU0_project
开源协议:
下载