项目描述 ：
This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.

高级语言： Verilog

项目主页：

项目地址: git://github.com/SaKi1309/Bit_Error_Tester.git

创建时间： 2021-01-27T13:12:34Z
项目社区：https://github.com/SaKi1309/Bit_Error_Tester
开源协议：MIT License
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