项目作者: manish-kj

项目描述 :
Universal number Posit HDL Arithmetic Architecture generator
高级语言: Verilog
项目地址: git://github.com/manish-kj/Posit-HDL-Arithmetic.git
创建时间: 2017-11-27T09:39:16Z
项目社区:https://github.com/manish-kj/Posit-HDL-Arithmetic

开源协议:BSD 3-Clause "New" or "Revised" License

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