智慧物流 spydrnet 返回
项目作者： byuccl

项目描述 ：
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
高级语言： Python
项目地址: git://github.com/byuccl/spydrnet.git
创建时间： 2019-09-23T15:25:09Z
项目社区：https://github.com/byuccl/spydrnet
开源协议：BSD 3-Clause "New" or "Revised" License
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ExampleCircuit_1648248417393.pdf
IR_1648248417408.pdf
flow_1648248417466.pdf
hierarchical_netlist_1648248417521.pdf
spydrnet_logo_1648248417574.pdf
IR_1648248417440.pptx
flow_1648248417506.pptx
hierarchical_netlist_1648248417536.pptx
spydrnet_logo_1648248417588.pptx
spydrnet_logo_2_1648248417619.pptx
spydrnet_logo_1649447404031.pptx
spydrnet_logo_2_1649447404312.pptx
flow_1649447403356.pptx
hierarchical_netlist_1649447403709.pptx
flow_1649447403095.pdf
hierarchical_netlist_1649447403496.pdf
spydrnet_logo_1649447403829.pdf
IR_1649447402865.pptx
ExampleCircuit_1649447402283.pdf
IR_1649447402599.pdf