PLC/vPLC cello 返回
项目作者： CIDARLAB

项目描述 ：
Genetic circuit design automation
高级语言： Java
项目地址: git://github.com/CIDARLAB/cello.git
创建时间： 2015-12-12T00:28:18Z
项目社区：https://github.com/CIDARLAB/cello
开源协议：BSD 2-Clause "Simplified" License
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reus_INPUT_pBAD_OFF_1648294099544.pdf
reus_INPUT_pBAD_ON_1648294099623.pdf
reus_INPUT_pLuxStar_OFF_1648294099719.pdf
reus_INPUT_pLuxStar_ON_1648294099780.pdf
reus_INPUT_pTac_OFF_1648294099838.pdf
reus_INPUT_pTac_ON_1648294099872.pdf
reus_INPUT_pTet_OFF_1648294099919.pdf
reus_INPUT_pTet_ON_1648294099968.pdf
Cello_SI_v58_1648294195843.pdf
UsingCello_1648294197890.pdf
UsingCello_1649482883970.pdf
Cello_SI_v58_1649482882012.pdf
reus_INPUT_pTac_OFF_1649482758035.pdf
reus_INPUT_pTac_ON_1649482758179.pdf
reus_INPUT_pTet_OFF_1649482758375.pdf
reus_INPUT_pTet_ON_1649482758519.pdf
reus_INPUT_pBAD_OFF_1649482757323.pdf
reus_INPUT_pBAD_ON_1649482757555.pdf
reus_INPUT_pLuxStar_OFF_1649482757700.pdf
reus_INPUT_pLuxStar_ON_1649482757855.pdf