项目描述 ：
This project is to implement a combination lock on the FPGA board using VHDL language and finite state machine. There are some possible solutions are provided to address the problems including debounce, random number generation and combination check.

高级语言： VHDL

项目主页：

项目地址: git://github.com/yuanbo-peng/Combination-Lock.git

创建时间： 2019-11-01T16:30:47Z
项目社区：https://github.com/yuanbo-peng/Combination-Lock
开源协议：
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