项目描述 ：
A carry select adder is an arithmetic combinational logic circuit which adds two N- bit binary numbers and outputs their N-bit binary sum and a 1-bit carry.

高级语言： Verilog

项目主页：

项目地址: git://github.com/menna15/Carry-Select-Adder.git

创建时间： 2020-08-09T18:24:40Z
项目社区：https://github.com/menna15/Carry-Select-Adder
开源协议：GNU General Public License v3.0
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